Requirements for higher integration density in semiconductor device fabrication processes tend to cause an increase in speed variation of MOS transistors (hereinafter referred to simply as transistors wherever appropriate) that are incorporated in a semiconductor integrated circuit chip. On this account, it becomes necessary to provide a surplus design margin in the phase of designing a semiconductor integrated circuit, resulting in increases in chip area and power consumption and a decrease in chip performance (operating frequency). In contrast, as a practical parameter control methodology, there is a technique for implementing speed tuning (speed variation suppression) of transistors through regulation of power supply voltage VDD in a semiconductor integrated circuit chip after fabrication thereof.
The technique for speed variation suppression of transistors through regulation of power supply voltage VDD is known as adaptive voltage scaling (AVS). The use of adaptive voltage scaling (AVS) makes it possible to implement speed variation suppression of transistors while reducing a surplus design margin, i.e., while allowing reduction in chip area and power consumption. Further, with the use of adaptive voltage scaling (AVS), it is allowed to provide enhancement in performance (operating frequency) of a semiconductor chip. The adaptive voltage scaling (AVS) is recognized as an indispensable technique in view of the current technical trend toward further possible increase in transistor speed variation since higher levels of integration are demanded in semiconductor device fabrication processes. The technique of adaptive voltage scaling (AVS) is described in detail in Non-patent Document 1 indicated below, for example.
As in the case of the adaptive voltage scaling (AVS), for controlling the operating speed of a semiconductor integrated circuit and for coping with process variations or the like, it is necessary to dynamically control power supply voltage VDD so that a minimum level of power supply voltage VDD required for achieving the chip performance (operating frequency) concerned is applied to each internal circuit of the semiconductor integrated circuit. For this purpose, a measurement is made of a signal delay in a replica circuit having a delay time equivalent to that of an internal circuit critical path in the semiconductor integrated circuit, and according to the result measured, the power supply voltage VDD is so controlled as to allow a signal to propagate through the replica circuit within a predetermined cycle time.
In Patent Document 1 indicated below, there is disclosed a technique for alleviating difficulty in the designing of a replica circuit through elimination of a replica circuit margin in the light of situations where just a single critical path is not necessarily provided, i.e., a plurality of critical paths having a substantially equal delay time are provided. According to the disclosure described in the Patent Document 1 indicated below, one of a plurality of transmission paths is selectively arranged as a critical path suitable for the replica circuit concerned, and the replica circuit comprises a circuit equivalent to a transmission path applicable as a critical path. More specifically, in the replica circuit, there are included a transmission path corresponding to a low-threshold-voltage transistor and a transmission path corresponding to a high-threshold-voltage transistor. In some situations, the low-threshold-voltage transistor and the high-threshold-voltage transistor may be different in the rate of process variation, and in other situations, the low-threshold-voltage transistor and the high-threshold-voltage transistor may be different in the degree of adverse effect of process variation with respect to a delay time even if there is no difference in the rate of variation. Hence, in either of the instances of process variation distributions to the worst-case side and to the best-case side, the power supply voltage VDD is controlled with a transmission path having a larger delay regardless of which one of the two transmission paths is arranged as a critical path.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2000-133772
[Non-patent document 1]
Mohamed Elgebaly et al., “Variation-Aware Adaptive Voltage Scaling System”, IEEE TRANSACTION ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 15, No. 5, May 2007, pp. 560 to 571.